1. Field of the Invention
The present invention relates generally to methods and cleaner compositions for forming residue free layers within microelectronic fabrications. More particularly, the present invention relates to methods and cleaner compositions for forming copper containing residue layer free microelectronic layers in the presence of copper containing conductor layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronic fabrication to employ when forming patterned microelectronic conductor layers within microelectronic fabrications, such as but not limited to patterned microelectronic conductor contact layers and patterned microelectronic conductor interconnect layers within microelectronic fabrications, copper containining conductor materials.
Copper containining conductor materials are desirable when forming patterned microelectronic conductor layers within microelectronic fabrications since copper containining conductor materials typically possess enhanced electrical properties in comparison with other conductor materials, such as but not limited to aluminum containing conductor materials and tungsten containing conductor materials, which may alternatively be employed for forming patterned microelectronic conductor layers within microelectronic fabrications.
While copper containining conductor materials are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers within microelectronic fabrications, copper containing conductor materials are not without problems within the art of microelectronic fabrication for forming patterned microelectronic conductor layers within microelectronic fabrications. In that regard, insofar as copper containing conductor materials are often difficult to pattern while employing reactive ion etch (RIE) plasma etch methods as are otherwise conventional for forming patterned microelectronic conductor layers within microelectronic fabrications, such patterned microelectronic conductor layers when formed within microelectronic fabrications of copper containing conductor materials are often formed employing damascene methods, including but not limited to dual damascene methods.
As is understood by a person skilled in the art, within a damascene method a blanket copper containing conductor layer is formed into an aperture formed within a patterned microelectronic layer, where the aperture typically comprises a via and/or trench defined within a patterned microelectronic dielectric layer, and the excess of the blanket copper containing conductor layer above the aperture is planarized while employing a chemical mechanical polish (CMP) planarizing method to form within the aperture a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layer, such as a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor stud layer and/or a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor interconnect layer within the corresponding via and/or the corresponding trench defined by the patterned microelectronic dielectric layer.
While such chemical mechanical polish (CMP) planarizing methods are thus useful for forming within microelectronic fabrications chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layers within microelectronic fabrications, such chemical mechanical polish (CMP) planarizing methods in turn are also not entirely without problems in the art of microelectronic fabrication for forming chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layers within vias and/or trenches defined by patterned microelectronic dielectric layers within microelectronic fabrications. In that regard, it is also known in the art of microelectronic fabrication that a patterned copper containing microelectronic conductor layer, when formed employing a chemical mechanical polish (CMP) planarizing method, is often formed while providing a copper containing chemical mechanical polish (CMP) residue layer upon at least a portion of the microelectronic fabrication adjoining the patterned copper containing microelectronic conductor layer. Similarly, when etching through a passivation dielectric layer subsequently formed upon the chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layer a via to reach the chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layer formed employing the chemical mechanical polish (CMP) planarizing method, there is also often formed a copper containing via etch residue layer upon at least the sidewalls of the via. Such copper containing chemical mechanical polish (CMP) residue layers and copper containing via etch residue layers are in turn undesirable in the art of microelectronic fabrication since they often compromise the functionality or reliability of a microelectronic fabrication within which they are formed.
It is thus towards the goal of forming within the art of microelectronic fabrication microelectronic fabrications having formed therein copper containing residue layer free microelectronic layers in the presence of copper containing conductor layers, such as but not limited to copper containing via etch residue layer free layers and copper containing chemical mechanical polish (CMP) residue layer free microelectronic layers in the presence of copper containing conductor layers, that the present invention is directed.
Various methods and materials have been disclosed in the art of microelectronic fabrication for forming microelectronic fabrications and microelectronic structures with desirable properties within the art of microelectronic fabrication.
For example, Ng et al., in "Synthesis of Some Carbonyl Derivatives of BTA and Determination of Their Inhibitive Properties for Copper in 3% NaCl Solution," Corrosion Science and Protection Technology, Vol. 9(3), July 1997, pp. 201-04, discloses various nitrogen substituted benzotriazole (BTA) derivatives formed incident to reaction of benzotriazole (BTA) with various acid chlorides (i.e., C1-C4 n-alkyl acid chlorides, t-butyl acid chloride, p-tolyl acid chloride and glutaryl di-acid chloride). The various nitrogen substituted benzotriazole (BTA) derivatives typically exhibit improved corrosion protection for copper surfaces in comparison with the nitrogen unsubstituted benzotriazole (BTA) parent material from which they are derived.
In addition, Kadomura, in U.S. Pat. No. 5,281,304, discloses a method for forming within a microelectronic fabrication from a blanket copper containing conductor layer formed within the microelectronic fabrication a patterned copper containing conductor layer formed within the microelectronic fabrication, while avoiding oxidation of the patterned copper containing conductor layer when forming the patterned copper containing conductor layer from the blanket copper containing conductor layer within the microelectronic fabrication. The method employs: (1) converting the surface of the blanket copper containing conductor layer to an anti-oxidation copper containing material prior to forming the patterned copper containing conductor layer from the blanket copper containing conductor layer; and (2) de-converting the anti-oxidation copper containing material to copper after forming the patterned copper containing conductor layer from the blanket copper containing conductor layer.
Further, Brusic et al., in U.S. Pat. No. 5,316,5573, disclose a corrosion protecting material layer which may be employed for protecting from corrosion within a microelectronic fabrication a non-noble metal layer, such as a cobalt non-noble metal layer, as well as an aqueous solution which may be employed for forming the corrosion protecting material layer upon the non-noble metal layer. The corrosion protecting layer comprises a copper (I) composition with benzotriazole (BTA) which is deposited from the aqueous solution comprising copper (II) ions and benzotriazole (BTA).
Still further, Sasaki et al., in U.S. Pat. No. 5,770,095, disclose a chemical mechanical polish (CMP) planarizing method and a chemical mechanical polish (CMP) slurry composition for use when forming from a blanket conductor layer within a microelectronic fabrication a chemical mechanical polish (CMP) planarized patterned conductor layer within the microelectronic fabrication, where the chemical mechanical polish (CMP) planarized patterned conductor layer is formed with attenuated dishing within the chemical mechanical polish (CMP) planarized patterned conductor layer. The chemical mechanical polish (CMP) planarizing method and the chemical mechanical polish (CMP) slurry composition realize the foregoing objects by incorporating into the chemical mechanical polish (CMP) slurry composition employed within the chemical mechanical polish (CMP) planarizing method in addition to a chemical mechanical polish (CMP) etching agent a chemical mechanical polish (CMP) protective film forming agent, where when the blanket conductor layer is a blanket copper containing conductor layer the chemical mechanical polish (CMP) protective film forming agent may comprise benzotriazole (BTA) or a benzotriazole (BTA) derivative.
Yet still further, Ulrich et al., in U.S. Pat. No. 5,897,379, disclose a method for selectively removing from only edge portions of a substrate employed within a microelectronic fabrication portions of a blanket copper containing layer formed over the substrate employed within the microelectronic fabrication, while not oxidizing remaining portions of the blanket copper containing layer formed over non-edge portions of the substrate. The method employs a masking of selected central portions of the blanket copper containing layer formed over the substrate and a subsequent wet chemical etching of the unmasked portions of the blanket copper containing layer at the edge portions of the substrate.
Still yet further, Lee et al., in U.S. Pat. No. 5,865,900, disclose a method for removing from an integrated circuit microelectronic fabrication structure within an integrated circuit microelectronic fabrication a metal fluoropolymer residue layer. The method comprises a sequential multi-step method employing: (1) a chlorine containing plasma to first form from the metal fluoropolymer residue layer a chlorine containing plasma treated metal fluoropolymer residue layer, which is then removed from the microelectronic fabrication by stripping while employing; (2) an aqueous acid solution, followed by; (3) an organic solvent.
Finally, Graham, in U.S. Pat. No. 5,882,452, discloses a related pair of methods and materials for removing from within a microelectronic fabrication a conductor etch residue layer formed incident to reactive ion etch (RIE) etching a blanket conductor layer to form a patterned conductor layer within the microelectronic fabrication, while avoiding pitting of the patterned conductor layer within the microelectronic fabrication. The methods employ when stripping the conductor etch residue layer: (1) an aqueous ammonium fluoride solution preferably saturated with carbon dioxide; and/or (2) (a) an aqueous ammonium fluoride solution followed by, (b) an aqueous solution saturated with ozone.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications copper containing residue layer free microelectronic layers in the presence of copper containing conductor layers within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.